WB-trees
Author:
Affiliation:
1. National Taiwan University, Taipei, Taiwan
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3195970.3196137
Reference25 articles.
1. Symmetry within the sequence-pair representation in the context of placement for analog design
2. Using non-slicing topological representations for analog placement;Balasa F.;IEICE Trans. Fundamentals,2001
3. B*-Trees
4. Double patterning lithography-aware analog placement
5. T. Chiarella etal "Benchmarking SOI and bulk FinFET alternatives for planar CMOS scaling succession " Solid-State Electron. 2010. T. Chiarella et al. "Benchmarking SOI and bulk FinFET alternatives for planar CMOS scaling succession " Solid-State Electron. 2010.
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