Affiliation:
1. Cornell University, Ithaca, NY
Abstract
We hypothesize that performing processor-side analysis of load instructions, and providing this pre-digested information to memory schedulers judiciously, can increase the sophistication of memory decisions while maintaining a lean memory controller that can take scheduling actions quickly. This is increasingly important as DRAM frequencies continue to increase relative to processor speed. In this paper we propose one such mechanism, pairing up a processor-side load criticality predictor with a lean memory controller that prioritizes load requests based on ranking information supplied from the processor side. Using a sophisticated multi-core simulator that includes a detailed quad-channel DDR3 DRAM model, we demonstrate that this mechanism can improve performance significantly on a CMP, with minimal overhead and virtually no changes to the processor itself. We show that our design compares favorably to several state-of-the-art schedulers.
Funder
Division of Computing and Communication Foundations
International Business Machines Corporation
Intel Corporation
Division of Computer and Network Systems
Publisher
Association for Computing Machinery (ACM)
Cited by
2 articles.
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1. CLIP: Load Criticality based Data Prefetching for Bandwidth-constrained Many-core Systems;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28
2. Anatomy of GPU Memory System for Multi-Application Execution;Proceedings of the 2015 International Symposium on Memory Systems;2015-10-05