Improving data cache performance by pre-executing instructions under a cache miss

Author:

Dundas James,Mudge Trevor

Publisher

ACM Press

Cited by 96 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Decoupled Vector Runahead for Prefetching Nested Memory-Access Chains;IEEE Micro;2024-07

2. Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

3. RPG 2 : Robust Profile-Guided Runtime Prefetch Generation;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27

4. Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses;ACM Transactions on Architecture and Code Optimization;2024-03-23

5. Decoupled Vector Runahead;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

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