Optimizing effective interconnect capacitance for FPGA power reduction
Author:
Affiliation:
1. University of Toronto, Toronto, ON, Canada
2. Fujitsu Laboratories Limited, Kawasaki, Japan
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2554688.2554788
Reference17 articles.
1. N. Magen A. Kolodny U. Weiser and N. Shamir "Interconnect-power dissipation in a microprocessor " in SLIP '04 2004 pp. 7--13. 10.1145/966747.966750 N. Magen A. Kolodny U. Weiser and N. Shamir "Interconnect-power dissipation in a microprocessor " in SLIP '04 2004 pp. 7--13. 10.1145/966747.966750
2. High-performance and low-voltage challenges for sub-45nm microprocessor circuits;Krishnamurthy R.;ASICON,2005
3. A Global Interconnect Optimization Scheme for Nanometer Scale VLSI With Implications for Latency, Bandwidth, and Power Dissipation
4. Global Interconnect Width and Spacing Optimization for Latency, Bandwidth and Power Dissipation
5. ITRS 2011 Report;ITRS;{Online}. Available: http://www.itrs.net/Links/,2011
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