Affiliation:
1. The Pennsylvania State University, University Park, PA
Abstract
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down access times and lowering miss rates. However, it was only recently that the first exploration [26] on prefetching TLB entries ahead of their need was undertaken and a mechanism called Recency Prefetching was proposed. There is a large body of literature on prefetching for caches, and it is not clear how they can be adapted (or if the issues are different) for TLBs, how well suited they are for TLB prefetching, and how they compare with the recency prefetching mechanism.This paper presents the first detailed comparison of different prefetching mechanisms (previously proposed for caches) - arbitrary stride prefetching, and markov prefetching - for TLB entries, and evaluates their pros and cons. In addition, this paper proposes a novel prefetching mechanism, called Distance Prefetching, that attempts to capture patterns in the reference behavior in a smaller space than earlier proposals. Using detailed simulations of a wide variety of applications (56 in all) from different benchmark suites and all the SPEC CPU2000 applications, this paper demonstrates the benefits of distance prefetching.
Publisher
Association for Computing Machinery (ACM)
Reference28 articles.
1. Etch traces. http://memsys.cs.washington.edu/memsys/html/traces.html.]] Etch traces. http://memsys.cs.washington.edu/memsys/html/traces.html.]]
2. Pointer-intensive benchmark suite. http://www.cs.wisc.edu/austin/ptr-dist.html.]] Pointer-intensive benchmark suite. http://www.cs.wisc.edu/austin/ptr-dist.html.]]
3. The interaction of architecture and operating system design
4. D. Burger and T. Austin. The SimpleScalar Toolset Version 3.0. http://www.simplescalar.org.]] D. Burger and T. Austin. The SimpleScalar Toolset Version 3.0. http://www.simplescalar.org.]]
Cited by
27 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Enhancing Microarchitecture Performance through Synergistic Dynamic Branch Prediction and Cache Prefetching;2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom);2023-12-07
2. vPIM: Efficient Virtual Address Translation for Scalable Processing-in-Memory Architectures;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
3. Memory-Efficient Hashed Page Tables;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02
4. History table-based linear analysis method for DRAM-PCM hybrid memory system;The Journal of Supercomputing;2021-04-15
5. NeuMMU;Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems;2020-03-09