A Desktop Computer with a Reconfigurable Pentium®

Author:

Lu Shih-Lien L.1,Yiannacouras Peter2,Suh Taeweon3,Kassa Rolf1,Konow Michael1

Affiliation:

1. Intel Corporation

2. Universty of Toronto (intern at Intel Corp.)

3. Georgia Institute of Technology (intern at Intel Corp.)

Abstract

Advancements in reconfigurable technologies, specifically FPGAs, have yielded faster, more power-efficient reconfigurable devices with enormous capacities. In our work, we provide testament to the impressive capacity of recent FPGAs by hosting a complete Pentium ® in a single FPGA chip. In addition we demonstrate how FPGAs can be used for microprocessor design space exploration while overcoming the tension between simulation speed, model accuracy, and model completeness found in traditional software simulator environments. Specifically, we perform preliminary experimentation/prototyping with an original Socket 7 based desktop processor system with typical hardware peripherals running modern operating systems such as Fedora Core 4 and Windows XP; however we have inserted a Xilinx Virtex-4 in place of the processor that should sit in the motherboard and have used the Virtex-4 to host a complete version of the Pentium ® microprocessor (which consumes less than half its resources). We can therefore apply architectural changes to the processor and evaluate their effects on the complete desktop system. We use this FPGA-based emulation system to conduct preliminary architectural experiments including growing the branch target buffer and the level 1 caches. In addition, we experimented with interfacing hardware accelerators such as DES and AES engines which resulted in a 27x speedup.

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science

Reference29 articles.

1. Performance and energy benefits of instruction set extensions in an FPGA soft core

2. Butler T. R. 2006. http://bochs.sourceforge.net/doc/docbook/user/bochsrc.html. Butler T. R. 2006. http://bochs.sourceforge.net/doc/docbook/user/bochsrc.html.

3. Cadence. 1998. Cadence Incisive Palladium. http://www.cadence.com/quickturn/. Cadence. 1998. Cadence Incisive Palladium. http://www.cadence.com/quickturn/.

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Area-Efficient Near-Associative Memories on FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2015-01-23

2. A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications;International Journal of Embedded and Real-Time Communication Systems;2012-04

3. Carry-free vector-matrix multiplication on a dynamically reconfigurable optical platform;Applied Optics;2010-04-14

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