Code generation for fixed-point DSPs

Author:

Araujo Guido1,Malik Sharad2

Affiliation:

1. IC-UNICAMP, Campinas, Brazil

2. Princeton Univ., Princeton, NJ

Abstract

This paper examines the problem of code-generation for Digital Signal Processors (DSPs). We make two major contributions. First, for an important class of DSP architectures, we propose an optimal O(n) algorithm for the tasks of register allocation and instruction scheduling for expression trees. Optimality is guaranteed by sufficient conditions derived from a structural representation of the processor Instruction Set Architecture (ISA). Second, we develop heuristics for the case when basic blocks are Directed Acyclic Graphs (DAGs).

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Register coalescing techniques for heterogeneous register architecture with copy sifting;ACM Transactions on Embedded Computing Systems;2009-01

2. Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers;Transactions on High-Performance Embedded Architectures and Compilers II;2009

3. A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors;The Compiler Design Handbook;2007-12-07

4. Optimistic coalescing for heterogeneous register architectures;ACM SIGPLAN Notices;2007-07-13

5. The CBP Parameter: A Module Characterization Approach for DSP Software Optimization;The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology;2004-09

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