A low latency router supporting adaptivity for on-chip interconnects
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ACM Press
Cited by 71 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study;IEEE Access;2023
2. FPGA Implementations and Performance Analysis of Different Routing Algorithms for the 2D-Mesh Network-On-Chip;Recent Trends in Intelligence Enabled Research;2023
3. A Load Balancing Mechanism for 3D Network-on-Chip with Partially Vertically Connected Links;Technological Innovation for Connected Cyber Physical Spaces;2023
4. Design of New Scalable Network on Chip Architecture using Adaptive Group based Routing Algorithm;2022 IEEE 7th International conference for Convergence in Technology (I2CT);2022-04-07
5. FastTrackNoC: A NoC with FastTrack Router Datapaths;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04
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