Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques-Reference-Cited by-同舟云学术

Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques

Published:2016-05-18 Issue: Volume: Page:
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Container-title:Proceedings of the 26th edition on Great Lakes Symposium on VLSI
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Author:

Batra Nidhi¹,Sehgal Pawan¹,Kaushik Shashwat¹,Hashmi Mohammad S.¹,Bhalla Sudesh²,Grover Anuj²

Affiliation:

1. IIIT-Delhi, New Delhi, India

2. ST Microelectronics, Greater Noida, India

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2902961.2903005

Reference10 articles.

1. International Technology Roadmap for Semiconductors International technology roadmap for semiconductors 2004. International Technology Roadmap for Semiconductors International technology roadmap for semiconductors 2004.

2. R.Venkatraman R.Castagnetti and S.Ramesh "The Statistics of Device Variations and its Impact on SRAM Bitcell Performance Leakage and Stability " in 7th International Symposium on Quality Electronic Design (ISQED) 2006. 10.1109/ISQED.2006.134 R.Venkatraman R.Castagnetti and S.Ramesh "The Statistics of Device Variations and its Impact on SRAM Bitcell Performance Leakage and Stability " in 7th International Symposium on Quality Electronic Design (ISQED) 2006. 10.1109/ISQED.2006.134

3. D. Burnett K. Erington C. Subramanian and K. Baker "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits " Symposium on VLSl Technology Digest of Technical Papers pp. 15--16 1994. D. Burnett K. Erington C. Subramanian and K. Baker "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits " Symposium on VLSl Technology Digest of Technical Papers pp. 15--16 1994.

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