Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation
Author:
Affiliation:
1. Kyoto University, Kyoto, Japan
Funder
Japan Society for the Promotion of Science
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2902961.2903013
Reference23 articles.
1. OpenCores. http://www.opencores.org OpenCores. http://www.opencores.org
2. Leakage current reduction in CMOS VLSI circuits by input vector control
3. BTIarray: A Time-Overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability
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