Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis-Reference-Cited by-同舟云学术

Aging-Aware Gate-Level Modeling for Circuit Reliability Analysis

Published:2021-09 Issue:9 Volume:68 Page:4201-4207
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Zhang Zuodong^ORCID,Wang Runsheng^ORCID,Shen Xuguang^ORCID,Wu Dehuang,Zhang Jiayang,Zhang Zhe^ORCID,Wang Joddy,Huang Ru

Funder

National Key Research and Development Program of China

NSFC

Higher Education Discipline Innovation Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9520090/09488281.pdf?arnumber=9488281

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