Logic Diagnosis with Hybrid Fail Data

Author:

Pomeranz Irith1,Amyeen M. Enamul2

Affiliation:

1. Purdue University, West Lafayette, IN

2. Intel Corporation, Hillsboro, OR

Abstract

Yield improvement requires information about the defects present in faulty units. This information is derived by applying a logic diagnosis procedure to the fail data collected by a tester from faulty units. It is typical in the early stages of yield learning to find faulty units that produce excessive volumes of fail data. The current practice is to terminate the fail data collection and possibly discard the fail data already collected for the unit. An earlier study shows that a faulty unit may produce excessive volumes of fail data for some tests but not for others. Based on this observation, a possible solution is to collect full fail data only for tests where this is feasible and pass/fail information for other tests. For this approach to be practical, it is necessary to be able to perform logic diagnosis with hybrid fail data that consists of full fail data for some tests and only pass/fail information for other tests. The main challenge in designing such a procedure is to balance the use of the two types of data to produce accurate logic diagnosis results. This article describes a logic diagnosis procedure, from the class of procedures used by commercial tools, that addresses this challenge. Experimental results for benchmark circuits demonstrate the importance of pass/fail information in this scenario.

Funder

Semiconductor Research Corporation

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Component Fault Diagnosability of Hierarchical Cubic Networks;ACM Transactions on Design Automation of Electronic Systems;2023-03-19

2. Logic Diagnosis Based on Deep Learning for Multiple Faults;2022 19th International SoC Design Conference (ISOCC);2022-10-19

3. Pass/Fail Data for Logic Diagnosis under Bounded Transparent-Scan;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021

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