Bridging the Gap between RTL and Software Fault Injection

Author:

Laurent J.1,Deleuze C.1,Pebay-Peyroula F.2,Beroulle V.1

Affiliation:

1. LCIS, Grenoble Institute of Engineering (INP), Univ. Grenoble Alpes, Valence, France

2. CEA-LETI, Univ. Grenoble Alpes, Grenoble, France

Abstract

Protecting programs against hardware fault injection requires accurate software fault models. However, typical models, such as the instruction skip, do not take into account the microarchitecture specificities of a processor. We propose in this article an approach to study the relation between faults at the Register Transfer Level (RTL) and faults at the software level. The goal is twofold: accurately model RTL faults at the software level and materialize software fault models to actual RTL injections. These goals lead to a better understanding of a system's security against hardware fault injection, which is important to design effective and cost-efficient countermeasures. Our approach is based on the comparison between results from RTL simulations and software injections (using a program mutation tool). Various analyses are included in this article to give insight on the relevance of software fault models, such as the computation of a coverage and fidelity metric, and to link software fault models to hardware RTL descriptions. These analyses are applied on various single-bit and multiple-bit injection campaigns to study the faulty behaviors of a RISC-V processor.

Funder

French national program programme d'investissements d'Avenir, IRT Nanoelec ANR-10-AIRT-05

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller;2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS);2024-07-03

2. Microarchitectural Insights into Unexplained Behaviors Under Clock Glitch Fault Injection;Lecture Notes in Computer Science;2024

3. SEU Reliability Assessment Framework for COTS Many-core Processors;2022 International Conference on Microelectronics (ICM);2022-12-04

4. Exploration of Fault Effects on Formal RISC-V Microarchitecture Models;2022 Workshop on Fault Detection and Tolerance in Cryptography (FDTC);2022-09

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