A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping-Reference-Cited by-同舟云学术

A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping

Published:2017-02-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
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Author:

Liu Gai¹,Zhang Zhiru¹

Affiliation:

1. Cornell University, Ithaca, NY, USA

Funder

Defense Advanced Research Projects Agency

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3020078.3021735

Reference16 articles.

1. Majority-Inverter Graph: A New Paradigm for Logic Optimization

2. Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification Release 60413. http://www.eecs.berkeley.edu/alanmi/abc/. Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification Release 60413. http://www.eecs.berkeley.edu/alanmi/abc/.

3. FPGA Design Automation: A Survey

4. Complexity of the lookup-table minimization problem for FPGA technology mapping

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