Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Author:

Bacha Anys1,Teodorescu Radu1

Affiliation:

1. The Ohio State University

Funder

Defense Advanced Research Projects Agency

Division of Computing and Communication Foundations

Hewlett-Packard Development Company

Publisher

ACM

Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

2. Speculative guardband: exploiting critical-delay variations across cached instructions;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

3. DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04

4. Exploiting Reduced Voltage Margins: From Node- to the Datacenter-level;Computing at the EDGE;2022

5. Harnessing Voltage margins for Balanced Energy and Performance;Computing at the EDGE;2022

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