Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors-Reference-Cited by-同舟云学术

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Published:2013-06-23 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 40th Annual International Symposium on Computer Architecture
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Author:

Bacha Anys¹,Teodorescu Radu¹

Affiliation:

1. The Ohio State University

Funder

Defense Advanced Research Projects Agency

Division of Computing and Communication Foundations

Hewlett-Packard Development Company

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2485922.2485948

Reference30 articles.

1. Improving cache lifetime reliability at ultra-low voltages

2. Power efficiency for variation-tolerant multicore processors

3. An Integrated Quad-Core Opteron Processor

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