DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors-Reference-Cited by-同舟云学术

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DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors

Published:2022-04 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
language:
Short-container-title:

Author:

Yahya Jawad Haj¹,Kim Jeremie S.¹,Yaglikci A. Giray¹,Park Jisung¹,Rotem Efraim²,Sazeides Yanos³,Mutlu Onur¹

Affiliation:

1. ETH Zurich

2. Intel Corporation

3. University of Cyprus

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9773179/9773180/09773193.pdf?arnumber=9773193

Reference171 articles.

1. A Self-Tuning DVS Processor Using Delay-Error Detection and Correction

2. AUDIT: Stress Testing the Automatic Way;kim;Micro,2012

3. Efficient Sensitivity Calculations for Optimization of Power Delivery Network Impedance

4. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance;das;JSSC,2008

5. Intel Architecture, Code Name Skylake Deep Dive: A New Architecture to Manage Power Performance and Energy Efficiency;rotem;Intel Developer Forum,2015

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Architectural Design Model Guided On-Demand Power Management of Energy-Efficient GPGPU for SLAM;Journal of Circuits, Systems and Computers;2023-04-21

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