Author:
Kuo Chin-Cheng,Hu Wei-Yi,Chen Yi-Hung,Kuan Jui-Feng,Cheng Yi-Kan
Cited by
4 articles.
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1. Conclusion and Future Work;Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies;2020
2. Yield Estimation Techniques Related Work;Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies;2020
3. Resilient design of current steering DACs using a transistor level approach;Analog Integrated Circuits and Signal Processing;2016-09-15
4. Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs;Proceedings of the 25th edition on Great Lakes Symposium on VLSI;2015-05-20