1. CMOS digital integrated circuit, Analysis and design, Sung Mo Kang and Yusuf Libecci, Third Edition, Tata Mac Graw Hill.
2. Low power and area efficient design of vlsi circuit, International Journal of Scientific and Research Publications, Volume 3, Issue 4, April 2013.
3. Sleepy keeper approach for performance tuning in VLSI, International Journal of Electronics and Communication Engineering.
4. Q. Wang and S. Vrudhula, "Static power optimization of deep sub-micron CMOS circuits for dual VT technology," in Proc. ICCAD, Apr. 1998, pp. 490--496.
5. Leakage Power Reduction in CMOS VLSI Circuits, International Journal of Computer Applications (0975-8887) Volume 55- No.8, October 2012.