MCML Gate Design for Standard Cell Library
Author:
Affiliation:
1. PGMicro - Graduate Program on Microlectronics, Federal University of Rio Grande do Sul, Av. Bento Gonçalves, 9500, Porto Alegre -- Brazil
Funder
Conselho Nacional de Desenvolvimento Científico e Tecnológico
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2800986.2801016
Reference12 articles.
1. Design strategies for source coupled logic gates
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3. M. Alioto and G. Palumbo "Design of MUX XOR and D-latch SCL gates " in Proc. of Int'l Symp. on Circuits and Systems (ISCAS) 2003. M. Alioto and G. Palumbo "Design of MUX XOR and D-latch SCL gates " in Proc. of Int'l Symp. on Circuits and Systems (ISCAS) 2003.
4. An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization
5. Accurate delay models of CMOS CML circuits for design optimization
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