A Charge Pump PLL with Fast-locking Strategies Embedded in FPGA in 65nm CMOS Technology-Reference-Cited by-同舟云学术

A Charge Pump PLL with Fast-locking Strategies Embedded in FPGA in 65nm CMOS Technology

Published:2017 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2017 2nd International Conference on Communication and Information Systems - ICCIS 2017
language:
Short-container-title:

Author:

Yang Mingqian¹,Chen Lei¹,Li Xuewu¹,Zhang Yanlong¹

Affiliation:

1. Beijing Microelectronics Technology Institute, Beijing, P. R. China

Publisher

ACM Press

Reference12 articles.

1. Roland E. Best, Phase-Locked Loops: Design, Simulation, and Applications, Mc-Graw Hill Professional Publishing, 2007.

2. F. Gardner. Charge-Pump Phase-Lock Loops. In IEEE Transactions on Communications, 28, 11 (Nov. 1980), 1849-1858.

3. K. Woo, Y. Liu, E. Nam and D. Ham. Fast-Lock Hybrid PLL Combining Fractional- N and Integer-N Modes of Differing Bandwidths. In IEEE Journal of Solid-State Circuits, 43, 2 (Feb. 2008), 379-389.

4. W. H. Chiu, Y. H. Huang and T. H. Lin. A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops. In IEEE Journal of Solid-State Circuits, 45, 6 (Jun. 2010), 1137-1149.

5. Z. Ding, H. Liu and Q. Li. A phase-error cancellation technique for fast-lock PLL. 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, 2014, 1-3.

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Digital Closed-Loop Control System for MEMS Resonant Pressure Sensors Based on a Quadrature Phase-Locked Loop;IEEE Sensors Journal;2024-04-01

2. Preconcentration of Luteoloside from Coreopsis Tinctoria and Determination by Near-infrared Spectroscopy;CHINESE J ANAL CHEM;2020