Resource-Aware Throughput Optimization for High-Level Synthesis-Reference-Cited by-同舟云学术

Resource-Aware Throughput Optimization for High-Level Synthesis

Published:2015-02-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
language:
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Author:

Li Peng¹,Zhang Peng¹,Pouchet Louis-Noel²,Cong Jason¹

Affiliation:

1. University of California, Los Angeles, Los Angeles, CA, USA

2. The Ohio State University, Columbus, OH, USA

Funder

MARCO and DARPA

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2684746.2689065

Reference22 articles.

1. High-Level Synthesis for FPGAs: From Prototyping to Deployment

2. "Vivado HLS " http://www.xilinx.com/products/designtools/vivado/index.htm. "Vivado HLS " http://www.xilinx.com/products/designtools/vivado/index.htm.

3. B. D. T. Inc. "An independent evaluation of: High-level synthesis tools for xilinx FPGAs " http://www.bdti.com/MyBDTI/pubs/Xilinx_hlstcp.pdf 2010. B. D. T. Inc. "An independent evaluation of: High-level synthesis tools for xilinx FPGAs " http://www.bdti.com/MyBDTI/pubs/Xilinx_hlstcp.pdf 2010.

4. Automatic memory partitioning and scheduling for throughput and power optimization

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