A complete formal semantics of x86-64 user-level instruction set architecture-Reference-Cited by-同舟云学术

A complete formal semantics of x86-64 user-level instruction set architecture

Published:2019-06-08 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation
language:
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Author:

Dasgupta Sandeep¹,Park Daejun²,Kasampalis Theodoros¹,Adve Vikram S.¹,Roşu Grigore³

Affiliation:

1. University of Illinois at Urbana-Champaign, USA

2. Runtime Verification, USA

3. University of Illinois at Urbana-Champaign, USA / Runtime Verification, USA

Funder

Defense Advanced Research Projects Agency

National Science Foundation

Office of Naval Research

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3314221.3314601

Reference63 articles.

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2. 2017. Sail x86 ISA model. https://github.com/rems-project/sail/tree/sail2/x86. Last accessed: May 2 2019. 2017. Sail x86 ISA model. https://github.com/rems-project/sail/tree/sail2/x86. Last accessed: May 2 2019.

3. 2018. Angr: A powerful and user-friendly binary analysis platform! http://angr.io/. Last accessed: May 2 2019. 2018. Angr: A powerful and user-friendly binary analysis platform! http://angr.io/. Last accessed: May 2 2019.

4. 2018. Bug Reported in Intel Developer Zone: Possible errors in instruction semantics. https://software.intel.com/en-us/forums/intel-isa-extensions/topic/773342. Last accessed: May 2 2019. 2018. Bug Reported in Intel Developer Zone: Possible errors in instruction semantics. https://software.intel.com/en-us/forums/intel-isa-extensions/topic/773342. Last accessed: May 2 2019.

5. 2018. Bug Reported in Stoke: Modelling the behavior of flags which may or must take undef values. https://github.com/StanfordPL/stoke/issues/986. Last accessed: May 2 2019. 2018. Bug Reported in Stoke: Modelling the behavior of flags which may or must take undef values. https://github.com/StanfordPL/stoke/issues/986. Last accessed: May 2 2019.

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