Formalizing, Verifying and Applying ISA Security Guarantees as Universal Contracts

Author:

Huyghebaert Sander1ORCID,Keuchel Steven2ORCID,De Roover Coen2ORCID,Devriese Dominique3ORCID

Affiliation:

1. Vrije Universiteit Brussel & KU Leuven, Brussel, Belgium

2. Vrije Universiteit Brussel, Brussel, Belgium

3. KU Leuven, Leuven, Belgium

Funder

European Research Council

Publisher

ACM

Reference53 articles.

1. CTSRD-CHERI/Flute: RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance., 2022. URL https://github.com/ CTSRD-CHERI/Flute.

2. Dijkstra monads for free

3. VeriSmall: Verified Smallfoot Shape Analysis

4. ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS

5. Krste Asanović and David A Patterson. Instruction sets should be free: The case for risc-v. EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-146, 2014.

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