Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode

Author:

Ebrahimi-Azandaryani Farhad1ORCID,Akbari Omid2ORCID,Kamal Mehdi3ORCID,Afzali-Kusha Ali1ORCID,Pedram Massoud4ORCID

Affiliation:

1. University of Tehran, Tehran, Iran

2. Tarbiat Modares University, Jalal AleAhmad, Tehran, Iran

3. University of Tehran and University of Southern California, Los Angeles

4. University of Southern California, Los Angeles

Abstract

In this paper, two accuracy configurable adders capable of operating in approximate and exact modes are proposed. In the adders, which include a block-based carry propagate and a parallel prefix structure, the carry chains are cut off in the approximate mode limiting the carry chain depth to two blocks. In the case of parallel prefix adder, we propose a special carry generate tree equipped with a power gating means. In both of the proposed structures, the critical paths of the adders are not increased in the exact operating mode. Thus, the main objective of proposing these approximate adder structures is to present an accuracy configurable adder structure whose delay in the exact mode is almost the same as an exact adder. The efficacies of the proposed accuracy configurable adders are compared with some state-of-the-art adder structures using a 15nm CMOS technology. In addition, their efficacies are evaluated in two error-resilient applications. These studies show that the proposed carry-propagate adder has 22% (51%) lower energy consumption (error rate) compared to the best prior works. Also, the proposed parallel prefix adder provides, on average, 20% lower energy consumption compared to the exact parallel prefix adders.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Reference26 articles.

1. Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications

2. M. Kamal, A. Ghasemazar, A. Afzali-Kusha, and M. Pedram. 2014. Improving efficiency of extensible processors by using approximate custom instructions. In Proc. DATE.

3. Multi-level approximate accelerator synthesis under voltage island constraints;Zervakis G.;IEEE Trans. Circuits Syst. II, Exp. Briefs,2018

4. Circuit-Level Techniques for Logic and Memory Blocks in Approximate Computing Systemsx

5. Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder;ACM Transactions on Design Automation of Electronic Systems;2024-04-22

2. Synthesis of Approximate Parallel-Prefix Adders;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

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