Affiliation:
1. Imperial College London, UK
2. Inria, France
3. MPI-SWS, Germany
Abstract
Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment of its available features that are relevant for the
consistency
semantics of multi-threaded programs as well as the
persistency
semantics of programs interfacing with non-volatile memory.
We extend these formalisations to cover: (1) non-temporal writes, which provide higher performance and are used to ensure that updates are flushed to memory; (2) reads and writes to other Intel-x86 memory types, namely uncacheable, write-combined, and write-through; as well as (3) the interaction between these features. We develop our formal model in both operational and declarative styles, and prove that the two characterisations are equivalent. We have empirically validated our formalisation of the consistency semantics of these additional features and their subtle interactions by extensive testing on different Intel-x86 implementations.
Funder
UKRI
European Research Council
Publisher
Association for Computing Machinery (ACM)
Subject
Safety, Risk, Reliability and Quality,Software
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