Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery

Author:

Pathak Divya1,Homayoun Houman2,Savidis Ioannis1

Affiliation:

1. Drexel University, Philadelphia, PA, USA

2. George Mason University, Fairfax, VA, USA

Publisher

ACM

Reference12 articles.

1. M. Tavana D. Pathak M. Hajkazemi I. Savidis and H. Homayoun "Realizing Complixity-Effective On-Chip Power Delivery for Many-Core Platforms by Exploiting Optimized Mapping " Proceedings of the IEEE International Conference on Computer Design pp. 581--588 October 2015. 10.1109/ICCD.2015.7357168 M. Tavana D. Pathak M. Hajkazemi I. Savidis and H. Homayoun "Realizing Complixity-Effective On-Chip Power Delivery for Many-Core Platforms by Exploiting Optimized Mapping " Proceedings of the IEEE International Conference on Computer Design pp. 581--588 October 2015. 10.1109/ICCD.2015.7357168

2. W. Kim M. S. Gupta G. Wei and D. Brooks "System Level Analysis of Fast Per-Core DVFS Using On-chip Switching Regulators " Proceedings of the International Symposium on High Performance Computer Architecture pp. 123--134 February 2008. W. Kim M. S. Gupta G. Wei and D. Brooks "System Level Analysis of Fast Per-Core DVFS Using On-chip Switching Regulators " Proceedings of the International Symposium on High Performance Computer Architecture pp. 123--134 February 2008.

3. Load Balanced On-Chip Power Delivery for Average Current Demand

4. D. Pathak M. Hajkazemi M. Tavana H. Homayoun and I. Savidis "Energy Efficient On-Chip Power Delivery with Run-Time Voltage Regulator Clustering " Proceedings of the IEEE International Symposium on Circuits and Systems pp. 1210--1213 May 2016. D. Pathak M. Hajkazemi M. Tavana H. Homayoun and I. Savidis "Energy Efficient On-Chip Power Delivery with Run-Time Voltage Regulator Clustering " Proceedings of the IEEE International Symposium on Circuits and Systems pp. 1210--1213 May 2016.

5. Efficient operating system scheduling for performance-asymmetric multi-core architectures

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