Light-weight communications on Intel's single-chip cloud computer processor

Author:

van der Wijngaart Rob F.1,Mattson Timothy G.2,Haas Werner3

Affiliation:

1. Intel Corporation, Santa Clara, CA

2. Intel Corporation, DuPont, WA

3. Intel Corporation, Braunschweig, Germany

Abstract

Many-core chips are changing the way high-performance computing systems are built and programmed. As it is becoming increasingly difficult to maintain cache coherence across many cores, manufacturers are exploring designs that do not feature any cache coherence between cores. Communications on such chips are naturally implemented using message passing, which makes them resemble clusters, but with an important difference. Special hardware can be provided that supports very fast on-chip communications, reducing latency and increasing bandwidth. We present one such chip, the Single-Chip Cloud Computer (SCC). This is an experimental processor, created by Intel Labs. We describe two communication libraries available on SCC: RCCE and Rckmb. RCCE is a light-weight, minimal library for writing message passing parallel applications. Rckmb provides the data link layer for running network services such as TCP/IP. Both utilize SCC's non-cache-coherent shared memory for transferring data between cores without needing to go off-chip. In this paper we describe the design and implementation of RCCE and Rckmb. To compare their performance, we consider simple benchmarks run with RCCE, and MPI over TCP/IP.

Publisher

Association for Computing Machinery (ACM)

Reference17 articles.

1. The 48-core SCC Processor: the Programmer's View

2. T.G. Mattson B.A. Sanders and B.L. Massingill Patterns for Parallel Programming Addison Wesley Design Patterns series 2004. T.G. Mattson B.A. Sanders and B.L. Massingill Patterns for Parallel Programming Addison Wesley Design Patterns series 2004.

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