Quantifying Performance Bottlenecks of Stencil Computations Using the Execution-Cache-Memory Model-Reference-Cited by-同舟云学术

Quantifying Performance Bottlenecks of Stencil Computations Using the Execution-Cache-Memory Model

Published:2015-06-08 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 29th ACM on International Conference on Supercomputing
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Author:

Stengel Holger¹,Treibig Jan¹,Hager Georg¹,Wellein Gerhard¹

Affiliation:

1. Friedrich-Alexander University of Erlangen-Nuremberg, Erlangen, Germany

Funder

EXASTEEL

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2751205.2751240

Reference16 articles.

1. Data layout transformation for stencil computations on short-vector simd architectures," in Proceedings of the 20th International Conference on Compiler Construction: Part of the Joint European Conferences on Theory and Practice of Software, ser. CC'11/ETAPS'11. Berlin, Heidelberg;Henretty T.;Springer-Verlag,2011

2. Lecture Notes in Computer Science;Treibig J.,2010

3. Optimization and Performance Modeling of Stencil Computations on Modern Microprocessors

4. Understanding stencil code performance on multicore architectures

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