Introducing a Performance Model for Bandwidth-Limited Loop Kernels-Reference-Cited by-同舟云学术

Introducing a Performance Model for Bandwidth-Limited Loop Kernels

Published:2010 Issue: Volume: Page:615-624
ISSN:0302-9743
Container-title:Parallel Processing and Applied Mathematics
language:
Short-container-title:

Author:

Treibig Jan,Hager Georg

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-14390-8_64.pdf

Reference5 articles.

1. Intel Corporation: Intel 64 and IA-32 Architectures Optimization Reference Manual, Document Number: 248966–17 (2008)

2. AMD, Inc.: Software Optimization Guide for AMD Family 10h Processors. Document Number: 40546 (2008)

3. Treibig, J., Hager, G., Wellein, G.: Multi-core architectures: Complixities of performance prediction and the impact of cache topology (2009), http://arxiv.org/abs/0910.4865

4. Schönauer, W.: Scientific Supercomputing: Architecture and Use of Shared and Distributed Memory Parallel Computers. Self-edition, Karlsruhe (2000)

5. Jalby, W., Lemuet, C., Le Pasteur, X.: WBTK: a New Set of Microbenchmarks to Explore Memory System Performance for Scientific Computing. International Journal of High Performance Computing Applications 18, 211–224 (2004)

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