1. Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/. Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/.
2. Local search algorithms for timing-driven placement under arbitrary delay models
3. Bookshelf. http://vlsicad.eecs.umich.edu/BK/ISPD06bench/BookshelfFormat.txt. Bookshelf. http://vlsicad.eecs.umich.edu/BK/ISPD06bench/BookshelfFormat.txt.
4. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
5. Cplex. http://www-03.ibm.com/software/products/en/ibmilogcpleoptistud/. Cplex. http://www-03.ibm.com/software/products/en/ibmilogcpleoptistud/.