Rsyn

Author:

Flach Guilherme1,Fogaça Mateus1,Monteiro Jucemar1,Johann Marcelo1,Reis Ricardo1

Affiliation:

1. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

Funder

Conselho Nacional de Desenvolvimento Científico e Tecnológico

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Publisher

ACM

Reference45 articles.

1. Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/. Berkeley Logic Synthesis and Verification Group ABC: A System for Sequential Synthesis and Verification. http://www.eecs.berkeley.edu/~alanmi/abc/.

2. Local search algorithms for timing-driven placement under arbitrary delay models

3. Bookshelf. http://vlsicad.eecs.umich.edu/BK/ISPD06bench/BookshelfFormat.txt. Bookshelf. http://vlsicad.eecs.umich.edu/BK/ISPD06bench/BookshelfFormat.txt.

4. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design

5. Cplex. http://www-03.ibm.com/software/products/en/ibmilogcpleoptistud/. Cplex. http://www-03.ibm.com/software/products/en/ibmilogcpleoptistud/.

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1. A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

2. iPD: An Open-source intelligent Physical Design Toolchain;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. iEDA: An Open-source infrastructure of EDA;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

4. Task-Based Parallel Programming for Gate Sizing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-04

5. Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural Network;2022 23rd International Symposium on Quality Electronic Design (ISQED);2022-04-06

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