Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells

Author:

Shi Daohang1,Davoodi Azadeh1

Affiliation:

1. University of Wisconsin, Madison, WI, USA

Funder

National Science Foundation

Publisher

ACM

Reference15 articles.

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Routability-aware pin access optimization for monolithic 3D designs;Proceedings of the 39th International Conference on Computer-Aided Design;2020-11-02

2. Morphed Standard Cell Layouts for Pin Length Reduction;2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2019-07

3. Fast and precise routability analysis with conditional design rules;Proceedings of the 20th System Level Interconnect Prediction Workshop;2018-06-23

4. A Comparative Study of Local Net Modeling Using Machine Learning;Proceedings of the 2018 on Great Lakes Symposium on VLSI;2018-05-30

5. Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration;IPSJ Transactions on System LSI Design Methodology;2017

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