NoC contention analysis using a branch-and-prune algorithm

Author:

Dasari Dakshina1,Nikoli'c Borislav1,N'elis Vincent1,Petters Stefan M.1

Affiliation:

1. CISTER/INESC-TEC Research Center, Polytechnic Institute of Porto, Portugal

Abstract

“Many-core” systems based on a Network-on-Chip (NoC) architecture offer various opportunities in terms of performance and computing capabilities, but at the same time they pose many challenges for the deployment of real-time systems, which must fulfill specific timing requirements at runtime. It is therefore essential to identify, at design time, the parameters that have an impact on the execution time of the tasks deployed on these systems and the upper bounds on the other key parameters. The focus of this work is to determine an upper bound on the traversal time of a packet when it is transmitted over the NoC infrastructure. Towards this aim, we first identify and explore some limitations in the existing recursive-calculus-based approaches to compute the Worst-Case Traversal Time (WCTT) of a packet. Then, we extend the existing model by integrating the characteristics of the tasks that generate the packets. For this extended model, we propose an algorithm called “Branch and Prune” (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus-based approaches. Finally, we introduce a more general approach, namely “Branch, Prune and Collapse” (BPC) which offers a configurable parameter that provides a flexible trade-off between the computational complexity and the tightness of the computed estimate. The recursive-calculus methods and BP present two special cases of BPC when a trade-off parameter is 1 or ∞, respectively. Through simulations, we analyze this trade-off, reason about the implications of certain choices, and also provide some case studies to observe the impact of task parameters on the WCTT estimates.

Funder

European Social Fund

FCT and COMPETE

Fundação para a Ciência e a Tecnologia

National Funds through FCT and ERDF (European Regional Development Fund) through COMPETE

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Reference25 articles.

1. Networks on chips: a new SoC paradigm

2. J.-Y. L. Boudec. and P. Thiran. 2004. Network Calculus—A Theory of Deterministic Queuing Systems for the Internet. Springer. J.-Y. L. Boudec. and P. Thiran. 2004. Network Calculus—A Theory of Deterministic Queuing Systems for the Internet. Springer.

3. Virtual-channel flow control

4. The torus routing chip

5. Response Time Analysis of COTS-Based Multicores Considering the Contention on the Shared Memory Bus

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems;ACM Transactions on Design Automation of Electronic Systems;2023-04-03

2. Response-time analysis of mesh-based many-core systems;Journal of Systems Architecture;2023-01

3. Side-channel protected MPSoC through secure real-time networks-on-chip;Microprocessors and Microsystems;2019-07

4. The Column-Partition and Row-Partition Turn Model;2018 IEEE 42nd Annual Computer Software and Applications Conference (COMPSAC);2018-07

5. Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays;Real-Time Systems;2018-06-21

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3