E 3 CC: A memory error protection scheme with novel address mapping for subranked and low-power memories

Abstract

This study presents and evaluates E 3 CC (Enhanced Embedded ECC), a full design and implementation of a generic embedded ECC scheme that enables power-efficient error protection for subranked memory systems. It incorporates a novel address mapping scheme called Biased Chinese Remainder Mapping (BCRM) to resolve the address mapping issue for memories of page interleaving, plus a simple and effective cache design to reduce extra ECC traffic. Our evaluation using SPEC CPU2006 benchmarks confirms the performance and power efficiency of the E 3 CC scheme for subranked memories as well as conventional memories.