Affiliation:
1. Barcelona Supercomputing Center, Barcelona, Spain
Abstract
Previous studies in software transactional memory mostly focused on reducing the overhead of transactional read and write operations. In this article, we introduce
transaction coalescing
, a profile-guided compiler optimization technique that attempts to reduce the overheads of starting and committing a transaction by merging two or more small transactions into one large transaction. We develop a profiling tool and a transaction coalescing heuristic to identify candidate transactions suitable for coalescing. We implement a compiler extension to automatically merge the candidate transactions at the compile time. We evaluate the effectiveness of our technique using the hash table micro-benchmark and the STAMP benchmark suite. Transaction coalescing improves the performance of the hash table significantly and the performance of Vacation and SSCA2 benchmarks by 19.4% and 36.4%, respectively, when running with 12 threads.
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Information Systems,Software
Cited by
3 articles.
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1. The semantics of transactions and weak memory in x86, Power, ARM, and C++;ACM SIGPLAN Notices;2018-12-02
2. The semantics of transactions and weak memory in x86, Power, ARM, and C++;Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation;2018-06-11
3. Dynamic transaction coalescing;Proceedings of the 11th ACM Conference on Computing Frontiers;2014-05-20