Position-aware thread-level speculative parallelization for large-scale chip-multiprocessor
Author:
Affiliation:
1. Tsinghua University, Beijing, China
2. Tsinghua University, Beijing, China and Yangtze Delta Region Institute of Tsinghua University, ZheJiang, China
Funder
High Tech. R&D Program of China
Brain Inspired Computing Research of Tsinghua University
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2742854.2742866
Reference23 articles.
1. An openmp extension that supports thread-level speculation. Parallel and Distributed Systems;Aldea S.;IEEE Transactions on, PP(99): 1--1,2015
2. Managing Wire Delay in Large Chip-Multiprocessor Caches
3. TILE64 - Processor: A 64-Core SoC with Mesh Interconnect
4. Architectural support for scalable speculative parallelization in shared-memory multiprocessors
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