Diligent TLBs-Reference-Cited by-同舟云学术

Diligent TLBs

Published:2019-06-26 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the ACM International Conference on Supercomputing
language:
Short-container-title:

Author:

Elnawawy Hussein¹,Chowdhury Rangeen Basu Roy²,Awad Amro³,Byrd Gregory T.¹

Affiliation:

1. North Carolina State University

2. Intel Corporation

3. University of Central Florida

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3330345.3330363

Reference25 articles.

1. {n. d.}. Intel 64 and IA-32 Architectures Optimization Reference Manual. https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html {n. d.}. Intel 64 and IA-32 Architectures Optimization Reference Manual. https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html

2. {n. d.}. Intel Itanium Architecture Software Developer's Manual Volume 2. Section 4.1.1.1. https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-software-developer-rev-2-3-vol-2-manual.pdf {n. d.}. Intel Itanium Architecture Software Developer's Manual Volume 2. Section 4.1.1.1. https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-software-developer-rev-2-3-vol-2-manual.pdf

3. Efficient virtual memory for big memory servers

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Morrigan: A Composite Instruction TLB Prefetcher;MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture;2021-10-17

2. Unified-TP: A Unified TLB and Page Table Cache Structure for Efficient Address Translation;2020 IEEE 38th International Conference on Computer Design (ICCD);2020-10