Unified-TP: A Unified TLB and Page Table Cache Structure for Efficient Address Translation-Reference-Cited by-同舟云学术

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Unified-TP: A Unified TLB and Page Table Cache Structure for Efficient Address Translation

Published:2020-10 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE 38th International Conference on Computer Design (ICCD)
language:
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Author:

Ma Zhulin,Tan Yujuan,Jiang Hong,Yan Zhichao,Liu Duo,Chen Xianzhang,Zhuge Qingfeng,Sha Edwin Hsing-Mean,Wang Chengliang

Funder

Natural Science Foundation of Chongqing

Fundamental Research Funds for the Central Universities

Wuhan National Laboratory for Optoelectronics

National Natural Science Foundation of China

China Postdoctoral Science Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9282809/9283502/09283526.pdf?arnumber=9283526

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

2. Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02

3. Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing;IEEE Access;2023

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