Block matching hardware architecture for SATD-based successive elimination-Reference-Cited by-同舟云学术

Block matching hardware architecture for SATD-based successive elimination

Published:2017 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 30th Symposium on Integrated Circuits and Systems Design Chip on the Sands - SBCCI '17
language:
Short-container-title:

Author:

Cancellier Luiz Henrique¹,Seidel Ismael¹,Güntzel José Luís¹

Affiliation:

1. Federal University of Santa Catarina (UFSC), Florianópolis, Brazil

Funder

Brazilian Federal Agency for the Support and Evaluation of Graduate Education (CAPES)

Brazilian Council for Scientific and Technological Development (CNPq)

Publisher

ACM Press

Reference20 articles.

1. Tae Gyoung Ahn, YongHo Moon, and Jae Ho Kim. 2003. An improved multilevel successive elimination algorithm for fast full-search motion estimation. InIEEE International Conference on Image Process (ICIP), Vol. 2. II-351-4 vol.3.

2. Frank Bossen, Benjamin Bross, Karsten Suhring, and David Flynn. 2012. HEVC complexity and implementation analysis.IEEE Trans. on Circ. Syst. for Video Technology22, 12 (2012), 1685--1696.

3. Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, and Sumit Kumar Chatterjee. 2015. Parallel Architecture for Successive Elimination Block Matching Algorithm. InMotion Estimation for Video Coding.Studies in Computational Intelligence, Vol. 590. Springer International Publishing, 35--44.

4. X.Q. Gao, C.J. Duanmu, and C.R. Zou. 2000. A multilevel successive elimination algorithm for block matching motion estimation.IEEE Trans. on Image Process.9, 3 (Mar 2000), 501--504.

5. D. Grois, D. Marpe, A. Mulayoff, B. Itzhaky, and O. Hadar. 2013. Performance comparison of H.265/MPEG-HEVC, VP9, and H.264/MPEG-AVC encoders. In2013 Picture Coding Symposium (PCS).394--397.