Parallel Architecture for Successive Elimination Block Matching Algorithm-Reference-Cited by-同舟云学术

Parallel Architecture for Successive Elimination Block Matching Algorithm

Published:2015 Issue: Volume: Page:35-44
ISSN:1860-949X
Container-title:Motion Estimation for Video Coding
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Author:

Chakrabarti Indrajit,Batta Kota Naga Srinivasarao,Chatterjee Sumit Kumar

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-14376-7_4

Reference11 articles.

1. Do, V.L., Yun, K.Y.: A low-power VLSI architecture for full-search block-matching motion estimation. IEEE Trans. Circuits Syst. Video Technol. 8(4), 393–398 (1998)

2. Jong, H.-M., Chen, L.-G., Chiueh, T.-D.: Parallel architectures for 3-step hierarchical search block-matching algorithm. IEEE Trans. Circuits Syst. Video Technol. 4(4), 407–416 (1994)

3. Srinivasan, R., Rao, K.: Predictive coding based on efficient motion estimation. In: Proceedings IEEE ICC’84, pp. 521–526 (1984)

4. Pun, A., Hang, H.M., Schilling, D.L.: An efficient block matching algorithm for motion compensated coding. In: Proceedings International Conference Acoustics, Speech, and Signal Processing, pp. 25.4.1–25.4.4 (1987)

5. Yeo, H., Hu, Y.: A novel matching criterion and low power architecture for real-time based block based motion estimation. In: Proceedings ASAP’96, pp. 122–130, August 1996

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