A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology-Reference-Cited by-同舟云学术

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

Published:2017-06-18 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 54th Annual Design Automation Conference 2017
language:
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Author:

Xu Biying¹,Li Shaolan¹,Sun Nan¹,Pan David Z.¹

Affiliation:

1. ECE Department, University of Texas at Austin, Austin, TX, USA

Funder

National Science Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3061639.3062192

Reference20 articles.

1. "International technology roadmap for semiconductors available at: http://www.itrs.net/." "International technology roadmap for semiconductors available at: http://www.itrs.net/."

2. A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

3. A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

4. B. Drost M. Talegaonkar and P. K. Hanumolu "A 0.55 v 61db-snr 67db-sfdr 7mhz 4 th-order butterworth filter using ring-oscillator-based integrators in 90nm cmos " in IEEE International Solid-State Circuits Conference (ISSCC) 2012 pp. 360--362. B. Drost M. Talegaonkar and P. K. Hanumolu "A 0.55 v 61db-snr 67db-sfdr 7mhz 4 th-order butterworth filter using ring-oscillator-based integrators in 90nm cmos " in IEEE International Solid-State Circuits Conference (ISSCC) 2012 pp. 360--362.

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