Optimal 2-D cell layout with integrated transistor folding
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ACM Press
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm;ACM Transactions on Reconfigurable Technology and Systems;2024-02-12
2. CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02
3. Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm;2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2022-05-15
4. An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures;ACM Transactions on Reconfigurable Technology and Systems;2018-03-22
5. Automatic Cell Layout in the 7nm Era;Proceedings of the 2017 ACM on International Symposium on Physical Design;2017-03-19
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