Gate-level test generation for sequential circuits-Reference-Cited by-同舟云学术

Gate-level test generation for sequential circuits

Published:1996-10 Issue:4 Volume:1 Page:405-442
ISSN:1084-4309
Container-title:ACM Transactions on Design Automation of Electronic Systems
language:en
Short-container-title:ACM Trans. Des. Autom. Electron. Syst.

Author:

Cheng Kwang-Ting¹

Affiliation:

1. Univ. of California, Santa Barbara

Abstract

This paper discusses the gate-level automatic test pattern generation (ATPG) methods and techniques for sequential circuits. The basic concepts, examples, advantages, and limitations of representative methods are reviewed in detail. The relationship between gate-level sequential circuit ATPG and the partial scan design is also discussed.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Link

https://dl.acm.org/doi/pdf/10.1145/238997.238999

Reference86 articles.

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2. ABRAMOVICI M. BREUER M. A. AND FRIEDMAN A. D. 1990. Digital Systems Testing and Testable Design. IEEE Computer Society Press Los Alamitos CA. ABRAMOVICI M. BREUER M. A. AND FRIEDMAN A. D. 1990. Digital Systems Testing and Testable Design. IEEE Computer Society Press Los Alamitos CA.

3. Combinational ATPG theorems for identifying untestable faults in sequential circuits

4. AGRAWAL V. D. AND SETH S. C. 1988. Tutorial--Test Generation for VLSI Chips. IEEE Computer Society Press Ch. 3 Los Alamitos CA. AGRAWAL V. D. AND SETH S. C. 1988. Tutorial--Test Generation for VLSI Chips. IEEE Computer Society Press Ch. 3 Los Alamitos CA.

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