Efficient hardware implementation of cellular neural networks with powers-of-two based incremental quantization

Author:

Xu Xiaowei1,Lu Qing2,Wang Tianchen2,Liu Jinglan2,Hu Yu3,Shi Yiyu2

Affiliation:

1. University of Notre Dame and Huazhong University of Science and Technology, Wuhan, China

2. University of Notre Dame

3. Huazhong University of Science and Technology, Wuhan, China

Publisher

ACM

Reference29 articles.

1. Mixed signal SIMD processor array vision chip for real-time image processing

2. Image-processing algorithms realized by discrete-time cellular neural networks and their circuit implementations

3. L. O. Chua and T. Roska. Cellular neural networks and visual computing: foundations and applications. Cambridge university press 2002. L. O. Chua and T. Roska. Cellular neural networks and visual computing: foundations and applications. Cambridge university press 2002.

4. M. Courbariaux I. Hubara D. Soudry R. El-Yaniv and Y. Bengio. Binarized neural networks: Training deep neural networks with weights and activations constrained to+ 1 or-1. arXiv preprint arXiv:1602.02830 2016. M. Courbariaux I. Hubara D. Soudry R. El-Yaniv and Y. Bengio. Binarized neural networks: Training deep neural networks with weights and activations constrained to+ 1 or-1. arXiv preprint arXiv:1602.02830 2016.

5. cellular neural network based medical image segmentation using artificial bee colony algorithm

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Parallel architecture of power‐of‐two multipliers for FPGAs;IET Circuits, Devices & Systems;2020-02-28

2. Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit;ACM Journal on Emerging Technologies in Computing Systems;2018-10-31

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