TA-FTA
Author:
Affiliation:
1. National Chiao Tung University, Hsinchu, Taiwan
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2744769.2744914
Reference14 articles.
1. Gate delay modeling with multiple input switching for static (statistical) timing analysis
2. Statistical gate delay model considering multiple input switching
3. An efficient algorithm to verify generalized false paths
4. Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal Probability;2022 IEEE International Test Conference in Asia (ITC-Asia);2022-08
2. SlewFTA: Functional Timing Analysis Considering Slew Propagation;2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT);2022-04-18
3. Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
4. Coupling-Aware Functional Timing Analysis for Tighter Bounds;Proceedings of the on Great Lakes Symposium on VLSI 2017;2017-05-10
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