High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths-Reference-Cited by-同舟云学术

High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

Published:2015-06-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 52nd Annual Design Automation Conference
language:
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Author:

Campbell Keith A.¹,Vissa Pranay¹,Pan David Z.²,Chen Deming¹

Affiliation:

1. University of Illinois at Urbana-Champaign

2. University of Texas at Austin

Funder

Semiconductor Research Corporation

National Science Foundation

Center for Future Architectures Research

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2744769.2744851

Reference18 articles.

1. High-Level Synthesis for FPGAs: From Prototyping to Deployment

2. High-Level Synthesis: Past, Present, and Future

3. LegUp

4. J. Tryon "Quadded logic " Redundancy Techniques for Computing Systems 1962. J. Tryon "Quadded logic " Redundancy Techniques for Computing Systems 1962.

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