Novel Approximate Multiplier Designs for Edge Detection Application

Author:

Mannepalli Yashaswi1,Korede Viraj Bharadwaj1,Rao Madhav1

Affiliation:

1. International Institute of Information Technology Bangalore, Bangalore, India

Publisher

ACM

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Approximate Tree Multiplier Using Approximate Compressor for Image Processing Applications;IETE Journal of Research;2024-05-23

2. Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

3. PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

4. Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

5. OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

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