Unlocking fine-grain parallelism for AIG rewriting

Author:

Possani Vinicius1,Lu Yi-Shan2,Mishchenko Alan3,Pingali Keshav2,Ribas Renato1,Reis Andre1

Affiliation:

1. Universidade Federal do Rio Grande do Sul, Brazil

2. The University of Texas at Austin

3. University of California

Publisher

ACM

Reference23 articles.

1. Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. http://www-cad.eecs.berkeley.edu/~alanmi/abc. Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification . http://www-cad.eecs.berkeley.edu/~alanmi/abc.

2. Majority-Inverter Graph

3. DAG-aware circuit compression for formal verification

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1. Enhancing ASIC Technology Mapping via Parallel Supergate Computing;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. FineMap: A Fine-grained GPU-parallel LUT Mapping Engine;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

4. EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

5. Rethinking AIG Resynthesis in Parallel;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

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