Unlocking fine-grain parallelism for AIG rewriting
Author:
Affiliation:
1. Universidade Federal do Rio Grande do Sul, Brazil
2. The University of Texas at Austin
3. University of California
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3240765.3240861
Reference23 articles.
1. Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. http://www-cad.eecs.berkeley.edu/~alanmi/abc. Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification . http://www-cad.eecs.berkeley.edu/~alanmi/abc.
2. Majority-Inverter Graph
3. DAG-aware circuit compression for formal verification
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