Hybrid on-chip communication architectures for heterogeneous manycore systems-Reference-Cited by-同舟云学术

Hybrid on-chip communication architectures for heterogeneous manycore systems

Published:2018-11-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the International Conference on Computer-Aided Design
language:
Short-container-title:

Author:

Joardar Biresh Kumar¹,Doppa Janardhan Rao¹,Pande Partha Pratim¹,Marculescu Diana²,Marculescu Radu²

Affiliation:

1. Washington State University

2. Carnegie Mellon University

Funder

National Science Foundation

Army Research Office

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3240765.3243480

Reference22 articles.

1. On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

2. 3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training

3. H. Jang etal Bandwidth-efficient on-chip interconnect designs for GPGPUs Design Automation Conference (DAC) ACM/EDAC/IEEE CA . 1--6. 2015.. 10.1145/2744769.2744803 H. Jang et al. Bandwidth-efficient on-chip interconnect designs for GPGPUs Design Automation Conference (DAC) ACM/EDAC/IEEE CA . 1--6. 2015.. 10.1145/2744769.2744803

4. BiNoCHS

5. J. Lee S. Li H. Kim and S. Yalamanchilli Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Heterogeneous Architecture Journal of Parallel Distributed Computing (JPDC) 1525--1538 2013. 10.1016/j.jpdc.2013.07.014 J. Lee S. Li H. Kim and S. Yalamanchilli Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Heterogeneous Architecture Journal of Parallel Distributed Computing (JPDC) 1525--1538 2013. 10.1016/j.jpdc.2013.07.014

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