Design space exploration of on-chip ring interconnection for a CPU–GPU heterogeneous architecture-Reference-Cited by-同舟云学术

Design space exploration of on-chip ring interconnection for a CPU–GPU heterogeneous architecture

Author:

Lee Jaekyu,Li Si,Kim Hyesoon,Yalamanchili Sudhakar

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference44 articles.

1. Achieving predictable performance through better memory controller placement in many-core cmps;Abts,2009

2. On characterizing performance of the cell broadband engine element interconnect bus;Ainsworth,2007

3. AMD, Fusion. http://sites.amd.com/us/fusion/apu/Pages/fusion.aspx, 2011.

4. Staged memory scheduling: achieving high performance and scalability in heterogeneous systems;Ausavarungnirun,2012

5. Throughput-effective on-chip networks for manycore accelerators;Bakhoda,2010

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