Filtering Translation Bandwidth with Virtual Caching-Reference-Cited by-同舟云学术

Filtering Translation Bandwidth with Virtual Caching

Published:2018-03-19 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems
language:
Short-container-title:

Author:

Yoon Hongil¹,Lowe-Power Jason²,Sohi Gurindar S.¹

Affiliation:

1. University of Wisconsin-Madison, Madison, WI, USA

2. University of California, Davis, Davis, CA, USA

Funder

University of Wisconsin Foundation (John P. Morgridge Professor)

National Science Foundation

William F. Vilas Trust Estate (Vilas Research Professor)

Wisconsin Alumni Research Foundation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3173162.3173195

Reference53 articles.

1. {n. d.}. AMD and HSA. ({n. d.}). Retrieved Accessed: 2017-12-09 from http://www.amd.com/en-us/innovations/software-technologies/hsa {n. d.}. AMD and HSA. ({n. d.}). Retrieved Accessed: 2017-12-09 from http://www.amd.com/en-us/innovations/software-technologies/hsa

2. {n. d.}. The ARM CoreLink CCI-550 Cache Coherent Interconnect. ({n. d.}). Retrieved Accessed: 2017-12-09 from https://developer.arm.com/products/system-ip/corelink-interconnect/corelink-cache-coherent-interconnect-family/corelink-cci-550 {n. d.}. The ARM CoreLink CCI-550 Cache Coherent Interconnect. ({n. d.}). Retrieved Accessed: 2017-12-09 from https://developer.arm.com/products/system-ip/corelink-interconnect/corelink-cache-coherent-interconnect-family/corelink-cci-550

3. High-bandwidth address translation for multiple-issue processors

4. Efficient virtual memory for big memory servers

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads;ACM Transactions on Architecture and Code Optimization;2024-09-14

2. IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

3. SnakeByte: A TLB Design with Adaptive and Recursive Page Merging in GPUs;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02

4. Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02

5. BARM: A Batch-Aware Resource Manager for Boosting Multiple Neural Networks Inference on GPUs With Memory Oversubscription;IEEE Transactions on Parallel and Distributed Systems;2022-12-01